Consider a paging system, it takes 10ns to search translation lookaside buffer (TLB) and 80ns to access main memory. If a law is new but its interpretation is vague, can the courts directly ask the drafters the intent and official interpretation of their law? So, t1 is always accounted. In this case, the second formula you mentioned is applicable because if L1 cache misses and L2 cache hits, then CPU access L2 cache in t2 time only and not (t1+t2) time. hit time is 10 cycles. (An average family has 2.3 children, but any real family has 0, 1, 2 or 3 children or an integer number of children; you don't see many 'three tenths of a child' wandering around). It is given that effective memory access time without page fault = i sec, = (1 / k) x { i sec + j sec } + ( 1 1 / k) x { i sec }. Why do small African island nations perform better than African continental nations, considering democracy and human development? This is the kind of case where all you need to do is to find and follow the definitions. By clicking Post Your Answer, you agree to our terms of service, privacy policy and cookie policy. Is there a solutiuon to add special characters from software and how to do it. Do roots of these polynomials approach the negative of the Euler-Mascheroni constant? Not the answer you're looking for? Please see the post again. - Inefficient memory usage and memory leaks put a high stress on the operating virtual memory subsystem. Making statements based on opinion; back them up with references or personal experience. The cache hit ratio can also be expressed as a percentage by multiplying this result by 100. as we shall see.) the CPU can access L2 cache only if there is a miss in L1 cache. 1. The TLB hit ratio is 90% and the page fault rate is one in every 10,000 instructions. Let us take the definitions given at Cache Performance by gshute at UMD as referenced in the question, which is consistent with the Wikipedia entry on average memory access time. It is given that effective memory access time without page fault = 20 ns. Which of the following is/are wrong? = 120 nanoseconds, In the case that the page is found in the TLB (TLB hit) the total time would be the time of search in the TLB plus the time to access memory, so, In the case that the page is not found in the TLB (TLB miss) the total time would be the time to search the TLB (you don't find anything, but searched nontheless) plus the time to access memory to get the page table and frame, plus the time to access memory to get the data, so, But this is in individual cases, when you want to know an average measure of the TLB performance, you use the Effective Access Time, that is the weighted average of the previous measures. For each page table, we have to access one main memory reference. The region and polygon don't match. Features include: ISA can be found Learn more about Stack Overflow the company, and our products. Actually, this is a question of what type of memory organisation is used. Assume that Question Using Direct Mapping Cache and Memory mapping, calculate Hit Ratio and effective access time of instruction processing. Is it possible to create a concave light? Acidity of alcohols and basicity of amines. contains recently accessed virtual to physical translations. The hierarchical organisation is most commonly used. Following topics of Computer Organization \u0026 Architecture Course are discussed in this lecture: What is Cache Hit, Cache Miss, Cache Hit Time, Cache Miss Time, Hit Ratio and Miss Ratio. (I think I didn't get the memory management fully). It looks like the solution depends on the definition of "the time to access the L1" and "the penalty to access L2 and main memory". Effective access time is a standard effective average. If TLB hit ratio is 60% and effective memory access time is 160 ns, TLB access time is ______. In Virtual memory systems, the cpu generates virtual memory addresses. Watch video lectures by visiting our YouTube channel LearnVidFun. * It is the first mem memory that is accessed by cpu. Effective Access time when multi-level paging is used: In the case of the multi-level paging concept of TLB hit ratio and miss ratio are the same. Windows)). ncdu: What's going on with this second size column? Thus, effective memory access time = 180 ns. If TLB hit ratio is 80%, the effective memory access time is _______ msec. \#2-a) Given Cache access time of 10ns, main memory of 100 ns And a hit ratio of 99% Find Effective Access Time (EAT). Write Through technique is used in which memory for updating the data? How many 32 K 1 RAM chips are needed to provide a memory capacity of 256 K-bytes ? The problem was: For a system with two levels of cache, define T c1 = first-level cache access time; T c2 = second-level cache access time; T m = memory access time; H 1 = first-level cache hit ratio; H 2 = combined first/second level cache hit ratio. The difference between the phonemes /p/ and /b/ in Japanese, How to handle a hobby that makes income in US. Does Counterspell prevent from any further spells being cast on a given turn? Practice Problems based on Page Fault in OS. It is a typo in the 9th edition. The average memory access time is the average of the time it takes to access a request from the cache and the time it takes to access a request from main . So the total time is equals to: And effective memory access time is equals to: Effective acess time Is total time spent in accessing memory( ie summation of main memory and cache acess time) divided by total number of memory references. Which has the lower average memory access time? A write of the procedure is used. Hence, it is fastest me- mory if cache hit occurs. What is the effective average instruction execution time? a) RAM and ROM are volatile memories Directions:Each of the items consist of two statements, one labeled as the Statement (I)'and the other as Statement (II) Examine these two statements carefully and select the answers to these items using the codes given below: Then, a 99.99% hit ratio results in average memory access time of-. It takes 20 ns to search the TLB and 100 ns to access the physical memory. Where: P is Hit ratio. nanoseconds) and then access the desired byte in memory (100 Integrated circuit RAM chips are available in both static and dynamic modes. Refer to Modern Operating Systems , by Andrew Tanembaum. There are two types of memory organisation- Hierarchical (Sequential) and Simultaneous (Concurrent). You can see another example here. Which of the following memory is used to minimize memory-processor speed mismatch? Example 1:Here calculating Effective memory Access Time (EMAT)where TLB hit ratio, TLB access time, and memory access time is given. If TLB hit ratio is 80%, the effective memory access time is _______ msec. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. Statement (II): RAM is a volatile memory. 2- As discussed here, we can calculate that using Teff = h1*t1 + (1-h1)*h2*t2 + (1-h1)*(1-h2)*t3 which yields 24. Or if we can assume it takes relatively ignorable time to find it is a miss in $L1$ and $L2$ (which may or may not true), then we might be able to apply the first formula above, twice. Due to the fact that the cache gets slower the larger it is, the CPU does this in a multi-stage process. Substituting values in the above formula, we get-, = 0.8 x{ 20 ns + 100 ns } + 0.2 x { 20 ns + (1+1) x 100 ns }. So, the L1 time should be always accounted. EAT := TLB_miss_time * (1- hit_ratio) + TLB_hit_time * hit_ratio. Assume no page fault occurs. The larger cache can eliminate the capacity misses. Informacin detallada del sitio web y la empresa: grupcostabrava.com, +34972853512 CB Grup - CBgrup, s una empresa de serveis per a la distribuci de begudes, alimentaci, productes de neteja i drogueria Assume that load-through is used in this architecture and that the b) Convert from infix to rev. This splits to two options: 50% the page to be dropped is clean, so the system just needs to read the new content: 50% the page to be dropped is dirty, so the system needs to write it to disk, Disk access time needed to read & bring in memory (from swapping area or pagefile) the PT itself, MEM time needed to access PT now in memory. The candidates appliedbetween 14th September 2022 to 4th October 2022. Formula to calculate the Effective Access Time: Effective Access Time =Cache Hit RatioCache Access. A cache is a small, fast memory that holds copies of some of the contents of main memory. Solution: Memory cost is calculated by; Ctotal= C1S1+C2S2+C3S3 G 15000, then S3=39.8 The effective memory access time is calculated as You'll get a detailed solution from a subject matter expert that helps you learn core concepts. So if a hit happens 80% of the time and a miss happens 20% of the time then the effective time (i.e. Regarding page directory (the first level of paging hierarchy) I believe it has to be always resident in RAM (otherwise, upon context switch, the x86 CR3 register content would be totally useless). Effective Memory Access Time = Cache access time * hit rate + miss rate * Miss penalty The above formula is too simple and given in many texts. It should be either, T = 0.8(TLB + MEM) + 0.2((0.9(TLB + MEM + MEM)) + 0.1(TLB + MEM + 0.5(Disk) + 0.5(2Disk + MEM))), T = 0.8(TLB + MEM) + 0.1(TLB + MEM + MEM) + 0.1(TLB + MEM + 0.5(Disk) + 0.5(2Disk + MEM)). It follows that hit rate + miss rate = 1.0 (100%). Is it plausible for constructed languages to be used to affect thought and control or mold people towards desired outcomes? If TLB hit ratio is 50% and effective memory access time is 170 ns, main memory access time is ______. It only takes a minute to sign up. TLB hit ratio- A TLB hit is the no of times a virtual-to-physical address translation was already found in the TLB, instead of going all the way to the page table which is located in slower physical memory. The result would be a hit ratio of 0.944. If Cache has 4 slots and memory has 90 blocks of 16 addresses each (Use as much required in question). In a multilevel paging scheme using TLB, the effective access time is given by-. Assume no page fault occurs. What is a word for the arcane equivalent of a monastery? 200 Find centralized, trusted content and collaborate around the technologies you use most. The static RAM is easier to use and has shorter read and write cycles. Now, substituting values in the above formula, we get- Effective access time with page fault = 10 -6 x { 20 ns + 10 ms } + ( 1 - 10 -6 ) x { 20 ns } = 10 -6 x 10 ms + 20 ns = 10 -5 ms + 20 ns = 10 ns + 20 ns = 30 ns Then the above equation becomes effective-access-time = cache-access-time + miss-rate * miss-penalty If Cache , for example, means that we find the desire page number in the TLB 80% percent of the time. Redoing the align environment with a specific formatting. Paging is a non-contiguous memory allocation technique. All I have done is basically to clarify something you have known as well as showing how to select the right definition or formula to apply. This is better understood by. Miss penalty mean extra spent time beyond the time spent on checking and missing the faster caches. Q2. The cache access time is 70 ns, and the Why are non-Western countries siding with China in the UN? So, efficiency of cache = Decrease in memory access time Original memory access time = 755 900 = 83.9 % Not sure if this is correct.. answered Nov 6, 2015 reshown Nov 9, 2015 by Arjun Arjun spawndon commented Jan 14, 2016 1 Arjun TLB hit ratio is nothing but the ratio of TLB hits/Total no of queries into TLB. Let the page fault service time be 10 ms in a computer with average memory access time being 20 ns. To learn more, see our tips on writing great answers. rev2023.3.3.43278. The fraction or percentage of accesses that result in a miss is called the miss rate. What sort of strategies would a medieval military use against a fantasy giant? Note: This two formula of EMAT (or EAT) is very important for examination. Which of the following loader is executed. can you suggest me for a resource for further reading? Assume that a given system's main memory has an access time of 6.0 ns, and its cache has an access.. Answer: To calculate: Hit ratio for effective access time of 1.5 ns. Effective memory Access Time (EMAT) for single-level paging with TLB hit ratio: Here hit ratio (h) = 80% means here taking 0.8, memory access time (m) = 80ns and TLB access time (t) = 10ns. has 4 slots and memory has 90 blocks of 16 addresses each (Use as How can this new ban on drag possibly be considered constitutional? The TLB is a high speed cache of the page table i.e. disagree with @Paul R's answer. The access time for L1 in hit and miss may or may not be different. Example 3:Here calculating the hit ratio, where EMAT, TLB access time, and memory access time is given. The best way to calculate a cache hit ratio is to divide the total number of cache hits by the sum of the total number of cache hits, and the number of cache misses. If it takes 100 nanoseconds to access memory, then a Principle of "locality" is used in context of. has 4 slots and memory has 90 blocks of 16 addresses each (Use as For example, if you have 51 cache hits and three misses over a period of time, then that would mean you would divide 51 by 54. Where TLB hit ratio is same single level paging because here no need access any page table, we get page number directly from TLB. Ltd.: All rights reserved. is executed using a 64KB cache, resulting in a hit rate of 97%, a hit time of 3 ns and the same miss penalty that in the previous case. A: Memory Read cycle : 100nsCache Read cycle : 20ns Four continuous reference is done - one reference. Full Course of Computer Organization \u0026 Architecture: https://youtube.com/playlist?list=PLV8vIYTIdSnar4uzz-4TIlgyFJ2m18NE3In this video you can learn about Cache Hit Time, Hit Ratio and Average Memory Access Time in Computer Organization \u0026 Architecture(COA) Course. [for any confusion about (k x m + m) please follow:Problem of paging and solution]. A sample program executes from memory But it is indeed the responsibility of the question itself to mention which organisation is used. Find centralized, trusted content and collaborate around the technologies you use most. 90% (of those 20%) of times the page is still mapped, but the address fell out of the cache, so we have to do extra memory read from the page map. It takes some computing resources, so it should actually count toward memory access a bit, but much less since the page faults don't need to wait for the writes to finish. If the page fault rate is 10% and dirty pages should be reloaded when needed, calculate the effective access time if: T = 0.8(TLB+MEM) + 0.2(0.9[TLB+MEM+MEM] + 0.1[TLB+MEM + 0.5(Disk) + 0.5(2Disk+MEM)]) = 15,110 ns. ERROR: CREATE MATERIALIZED VIEW WITH DATA cannot be executed from a function. Your answer was complete and excellent. That is. A notable exception is an interview question, where you are supposed to dig out various assumptions.). However, we could use those formulas to obtain a basic understanding of the situation. Virtual Memory The exam was conducted on 19th February 2023 for both Paper I and Paper II. Browse other questions tagged, Start here for a quick overview of the site, Detailed answers to any questions you might have, Discuss the workings and policies of this site. Substituting values in the above formula, we get-, = 0.0001 x { 1 sec + 10 msec } + 0.99999x 1 sec, If an instruction takes i microseconds and a page fault takes an additional j microseconds, the effective instruction time if on the average a page fault occurs every k instruction is-. That would be true for "miss penalty" (miss time - hit time), but miss time is the total time for a miss so you shouldn't be counting the hit time on top of that for misses. EAT := (TLB_search_time + 2*memory_access_time) * (1- hit_ratio) + (TLB_search_time + memory_access_time)* hit_ratio. A single-level paging system uses a Translation Look-aside Buffer (TLB) where memory access takes 100ns and hit ratio of TLB 80%. Assume no page fault occurs. What is . But in case ofTLB miss when the page number is not present at TLB, we have to access the page table and if it is a multi-level page table, we require to access multi-level page tables for the page number. Why do many companies reject expired SSL certificates as bugs in bug bounties? The address field has value of 400. If found, it goes to the memory location so the total access time is equals to: Now if TLB is missing then you need to first search for TLB, then for the page table which is stored into memory. Here it is multi-level paging where 3-level paging means 3-page table is used. Effective access time is increased due to page fault service time. Average Access Time is hit time+miss rate*miss time, Effective memory Access Time (EMAT) for single level paging with TLB hit ratio: Here hit ratio =80% means we are taking0.8,memory access time (m) =100ns,Effective memory Access Time (EMAT) =140ns and letTLB access time =t. A single-level paging system uses a Translation Look-aside Buffer (TLB). So, here we access memory two times. The cycle time of the processor is adjusted to match the cache hit latency. And only one memory access is required. A page fault occurs when the referenced page is not found in the main memory. Also, TLB access time is much less as compared to the memory access time. 170 ns = 0.5 x{ 20 ns + T ns } + 0.5 x { 20 ns + (1+1) x T ns }, 170 ns = 0.5 x { 20 ns + T ns } + 0.5 x { 20 ns + 2T ns }. It takes 20 ns to search the TLB. Example 4:Here calculating TLB access time, where EMAT, TLB hit ratio and memory access time is given. Is it possible to create a concave light? So one memory access plus one particular page acces, nothing but another memory access. A page fault occurs when the referenced page is not found in the main memory. Part B [1 points] Can archive.org's Wayback Machine ignore some query terms? The idea of cache memory is based on ______. cache is initially empty. first access memory for the page table and frame number (100 The nature of simulating nature: A Q&A with IBM Quantum researcher Dr. Jamie We've added a "Necessary cookies only" option to the cookie consent popup. The total cost of memory hierarchy is limited by $15000. By clicking Accept all cookies, you agree Stack Exchange can store cookies on your device and disclose information in accordance with our Cookie Policy. Connect and share knowledge within a single location that is structured and easy to search. k number of page tables are present, and then we have to accessan additional k number of main memory access for the page table. Are those two formulas correct/accurate/make sense? If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 6 array, where each chip is 8K 4 bits? It is given that one page fault occurs every k instruction. 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Hit ratio: r = N hit N hit + N miss Cache look up cost: C cache = rC h + (1 r) Cm Cache always improves performance when Cm > C h and r > 0. 160 ns = 0.6 x{ T ns + 100 ns } + 0.4 x { T ns + (1+1) x 100 ns }, 160 ns = 0.6 x { T ns + 100 ns } + 0.4 x { T ns + 200 ns }, 160 ns = 0.6T ns + 60 ns + 0.4T ns + 80 ns, 0.6T ns + 0.4T ns = 160 ns 60 ns 80 ns. Calculation of the average memory access time based on the following data? = 0.8 x{ 20 ns + 100 ns } + 0.2 x { 20 ns + (2+1) x 100 ns }. But, in sequential organisation, CPU is concurrently connected all memory levels and can access them simultaneously. Word size = 1 Byte. Here it is multi-level paging where 3-level paging means, level of paging is not mentioned, we can assume that it is, and Effective memory Access Time (EMAT) =, Difference between system call and library call, Hybrid Kernel and Nano Kernel or Pico Kernel, Long Term, Short-term and Mid-term Scheduler, Shortest Remaining Time First (SRTF) (Preemptive SJF), Special Example of SRTF with CPU and I/O Time, Inter-process communication and Synchronization, Process Synchronization as a solution of Critical Section, Requirement of Synchronization mechanisms, Lock variable with priority Inversion Problem, Comparison: synchronization solutions with busy waiting, Producer and Consumer problem with Race Condition, Solving the Producer-Consumer Problem Using Semaphores, NET and GATE question: Counting Semaphore, Binary Semaphore question on NET and GATE, Producer-Consumer Problem Using Semaphores, Dining Philosopher Problem algorithm and example, Barrier synchronism algorithm and example, Precedence graph for concurrency programming, Advantages and disadvantages Dynamic Linking, Related Questions: SET, NET, GATE and ISRO, Solution of External Fragmentation: Compaction, Algorithms for finding appropriate Holes in Memory, Protection in Contiguous Memory Allocation, Concept of Non-contiguous memory allocation, Calculation of Logical Address Bit and number of Pages, Calculation of Physical Address Bit and number of Frames, Effective Access Time using Hit & Miss Ratio, GATE and NET question on calculation EMAT, GATE/NET question on EMAT with Page fault, GATE/NET question on EMAT with Page Fault, Concept: Optimal page replacement algorithm, GATE Question: FIFO page replacement algorithm. If we fail to find the page number in the TLB then we must A cache is a small, fast memory that is used to store frequently accessed data. Posted one year ago Q: Q: Consider a memory system with a cache access time of 100ns and a memory access time of 1200ns. You will find the cache hit ratio formula and the example below. This is due to the fact that access of L1 and L2 start simultaneously. How can I find out which sectors are used by files on NTFS? The nature of simulating nature: A Q&A with IBM Quantum researcher Dr. Jamie We've added a "Necessary cookies only" option to the cookie consent popup. d) A random-access memory (RAM) is a read write memory. What's the difference between cache miss penalty and latency to memory? Block size = 16 bytes Cache size = 64 Consider a single level paging scheme with a TLB. I agree with this one! Assume no page fault occurs. Using Verilog, designed a 16-block direct-mapped, write-back cache with 2 words/line, that supports same cycle read/write hit. Browse other questions tagged, Where developers & technologists share private knowledge with coworkers, Reach developers & technologists worldwide, Thank you. A hit occurs when a CPU needs to find a value in the system's main memory. Follow Up: struct sockaddr storage initialization by network format-string, Short story taking place on a toroidal planet or moon involving flying, Bulk update symbol size units from mm to map units in rule-based symbology, Minimising the environmental effects of my dyson brain. Linux) or into pagefile (e.g. EAT(effective access time)= P x hit memory time + (1-P) x miss memory time. You can see further details here. Site design / logo 2023 Stack Exchange Inc; user contributions licensed under CC BY-SA. The effective time here is just the average time using the relative probabilities of a hit or a miss. The cache access time is 70 ns, and the time for transferring a main memory block to the cache is 3000 ns. To learn more, see our tips on writing great answers. Provide an equation for T a for a read operation. Consider a single level paging scheme with a TLB. Senior Systems Engineer with a unique combination of skills honed over more than 20 years and cross-functional and holistic IT Core Infrastructure, Virtualization, Network, Cloud, Hybrid, DC . It is a question about how we interpret the given conditions in the original problems. (A) 120(B) 122(C) 124(D) 118Answer: (B)Explanation: TLB stands for Translation Lookaside Buffer. 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Due to locality of reference, many requests are not passed on to the lower level store. A tiny bootstrap loader program is situated in -. What will be the EAT if hit ratio is 70%, time for TLB is 30ns and access to main memory is 90ns? Assume no page fault occurs. Can you provide a url or reference to the original problem? It is a question about how we translate the our understanding using appropriate, generally accepted terminologies. Let Cache Hit ratio be H, Given, Access time of main memory = Amain = 6.0 ns Access time of cache memory =. Average memory access time = (0.1767 * 50) + (0.8233 * 70) = 66.47 sec. Answer: the Wikipedia entry on average memory access time, We've added a "Necessary cookies only" option to the cookie consent popup, 2023 Moderator Election Q&A Question Collection, calculate the effective (average) access time (E AT) of this system, Finding cache block transfer time in a 3 level memory system, Computer Architecture, cache hit and misses, Pros and Cons of Average Memory Access Time When Increasing Cache Block Size. Daisy wheel printer is what type a printer? 4. Start Now Detailed Solution Download Solution PDF Concept: The read access time is given as: T M = h T C + (1 - h) T P T M is the average memory access time T C is the cache access time T P is the access time for physical memory h is the hit ratio Analysis: Given: H = 0.9, T c = 100, T m = 1000 Now read access time = HTc + (1 - H) (Tc + Tm) average time) over a large number of hits/misses will be 0.8 * (hit time) + 0.2 * (miss time). Now, substituting values in the above formula, we get-, = 10-6 x { 20 ns + 10 ms } + ( 1 10-6 ) x { 20 ns }, Suppose the time to service a page fault is on the average 10 milliseconds, while a memory access takes 1 microsecond. Thus it exist a percentage of occurrences we have to include at least: Thanks for contributing an answer to Stack Overflow! So, a special table is maintained by the operating system called the Page table. However, that is is reasonable when we say that L1 is accessed sometimes. Evaluate the effective address if the addressing mode of instruction is immediate? That splits into further cases, so it gives us. So, the percentage of time to fail to find the page number in theTLB is called miss ratio. The average access time of the system for both read and write requests is, TPis the access time for physical memory, = (0.8 200 + 0.2 1000) nsec = 360 nsec. Note: We can use any formula answer will be same. For example,if we have 80% TLB hit ratio, for example, means that we find the desire page number in the TLB 80% percent of the time. What's the difference between a power rail and a signal line? In the hierarchical organisation all the levels of memory (cache as well as main memory) are connected sequentially i.e. percentage of time to fail to find the page number in the, multi-level paging concept of TLB hit ratio and miss ratio, page number is not present at TLB, we have to access, page table and if it is a multi-level page table, we require to access multi-level page tables for. Does a summoned creature play immediately after being summoned by a ready action? Do new devs get fired if they can't solve a certain bug? The CPU checks for the location in the main memory using the fast but small L1 cache. we need to place a physical memory address on the memory bus to fetch the data from the memory circuitry. How to react to a students panic attack in an oral exam? Difference between system call and library call, Hybrid Kernel and Nano Kernel or Pico Kernel, Long Term, Short-term and Mid-term Scheduler, Shortest Remaining Time First (SRTF) (Preemptive SJF), Special Example of SRTF with CPU and I/O Time, Inter-process communication and Synchronization, Process Synchronization as a solution of Critical Section, Requirement of Synchronization mechanisms, Lock variable with priority Inversion Problem, Comparison: synchronization solutions with busy waiting, Producer and Consumer problem with Race Condition, Solving the Producer-Consumer Problem Using Semaphores, NET and GATE question: Counting Semaphore, Binary Semaphore question on NET and GATE, Producer-Consumer Problem Using Semaphores, Dining Philosopher Problem algorithm and example, Barrier synchronism algorithm and example, Precedence graph for concurrency programming, Advantages and disadvantages Dynamic Linking, Related Questions: SET, NET, GATE and ISRO, Solution of External Fragmentation: Compaction, Algorithms for finding appropriate Holes in Memory, Protection in Contiguous Memory Allocation, Concept of Non-contiguous memory allocation, Calculation of Logical Address Bit and number of Pages, Calculation of Physical Address Bit and number of Frames, Effective Access Time using Hit & Miss Ratio, GATE and NET question on calculation EMAT, GATE/NET question on EMAT with Page fault, GATE/NET question on EMAT with Page Fault, Concept: Optimal page replacement algorithm, GATE Question: FIFO page replacement algorithm.
